We are looking for a highly skilled Verification Engineer with expertise in Universal Verification Methodology (UVM), and preferably with knowledge in FPGA, to join our advanced team in Eindhoven. In this role, you will focus on verifying complex FPGA designs, ensuring they meet rigorous performance, functionality, and reliability standards. Working alongside a multidisciplinary team, you will play a key role in ensuring the quality and robustness of our FPGA-based solutions.
Key Responsibilities:
- Develop and implement UVM-based verification environments to validate FPGA designs.
- Define verification strategies, plans, and test scenarios based on design specifications.
- Create, simulate, and debug testbenches to verify design functionality and performance.
- Perform functional, code coverage, and assertion-based verification to ensure robust designs.
- Identify, debug, and resolve design issues through simulation and detailed analysis.
- Collaborate closely with FPGA designers to understand design intent and resolve verification bottlenecks.
- Document verification methodologies, results, and lessons learned to support future projects.
- Stay informed about advancements in UVM verification techniques and industry best practices.
- Plan and execute verification from scratch.
