Introduction
SMART Photonics B.V. is a pure-play Indium Phosphide (InP) photonic foundry. We work closely with customers across telecom, datacom, sensing, and quantum to turn innovative ideas into high-performance photonic integrated circuits (PICs).
Why this role exists:
As an InP foundry, SMART's strength is in frontend processing and device design. Our chips, however, must succeed inside packages built and qualified by our customers and partners. As product complexity and volumes grow we would like to enhance this connection between our frontend choices and the packaging realities: translating packaging requirements into design rules, assessing compatibility of our process modules with industry-standard packaging techniques, and ensuring our PICs are packaging-ready by construction. This will be the focus of this new senior individual contributor role within our Product & Integration Engineering (PIE) team.
The team you'll work with:
You'll join a strong and diverse PIE team!
Three Device Integration Engineers focused on EOL PCM, EOL data analysis, and understanding device-level design enablement; four Vertical Integration Engineers focused on process flow, in-line PCM, and issue resolution; and a dedicated statistician supporting data analysis across the value chain. You'll partner closely with our Design Enablement team, Test & Measurement Reliability team, Backend team as well as external partners for backend, packaging, and testing.
This is a role where collaboration skills are crucial for long-term success.
What you'll do:
Own the bridge between our frontend and packaging.
Establish and maintain Design-for-Packaging rules and process specifications that connect our InP foundry capabilities to the packaging techniques our customers and partners use. Translate learnings into PDK updates, in close collaboration with the Design Enablement team.
Assess process-to-packaging compatibility.
Evaluate whether our bondpads, planarization, metallization stacks, layout patterns, and other process modules are compatible with die attach, wire bonding, fiber alignment, and assembly methods used in the industry. Identify gaps and drive corrective actions through design or process changes.
Lead packaging-integration aspects of flagship programs.
We have several customer-partnership program, both at the advance stages where the focus is optimization and packaging compatibility for chips that are already processed and characterized as well as new platforms with the opportunity to influence designs for packaging readiness from an early stage. Examples are integrated iTLA and DFB demo programs.
Ensure that frontend-to-packaging decisions account for backend and reliability realities.
Coordinate with our Backend team (internal and outsourced via our future OSAT partner) on backend process implications, and with the T&M Reliability team on reliability outcomes. Evaluate supplier and partner results on pull and shear tests, qualification reports, design rule conformance, bring physics-aware interpretation to reliability data – all to make sure that both backend and reliability are well accounted in questions of packaging.
Drive yield improvement
By connecting packaging and reliability outcomes with in-line and EOL data across the value chain.
Lead cross-functional integration projects
Ensuring clear technical direction, alignment with stakeholders, and timely delivery.
